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The PSR combines three 32-bit registers – APSR, IPSR, and EPSR – as shown in Figure 2. The IPSR register is a part of the ARM Cortex-M0’s Program Status Register (PSR). Here is the IPSR bit assignment in detail (as per Cortex -M0 Devices Generic User Guide):įigure 1 : IPSR Register Definition (Source: ARM) The second method is to watch the Interrupt Program Status Register (IPSR). If this is a hard fault, the PC register will indicate operation in the hard fault handler. The first is to watch the Program Counter (PC) register.
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There are two ways to determine whether the hang up is due to the hard fault. To detect the cause for system hang up, first execute your program in debugging mode and allow the system to run until the system hangs up again, then halt the debugger. When your system is hung up, the first step is to detect the cause for the hang up. The most common user-created causes for hard fault are:Īttempted load or store to an unaligned address. System-generated bus error on a vector fetchĮxecution of an instruction from a location for which the system generates a bus faultĮxecution of an instruction when not in Thumb-State as a result of the T-bit being previously cleared to 0Īttempted load or store to an unaligned addressĮxecution of an instruction from an XN memory address System-generated bus error on a load or store As per the Cortex-M0 Devices Generic User Guide (revision r0p0), the following sources can cause a hard fault:Įxecution of an SVC instruction at a priority equal or higher than SVCallĮxecution of a BKPT instruction without a debugger attached
#HARD TIME PC DEBUG HOW TO#
In this article, we will discuss some common errors programmers make and how to debug the hard fault caused by these errors.Ī hard fault is an exception that occurs because of an error during normal or exception processing. However, most of the time chasing down a hard fault can be very time consuming. In some cases, we might get lucky and be able to quickly locate the source of the hard fault. One common issue developers face in Cortex-M0-based embedded systems is the hard fault. Programmable system-on-chip (PSoC) architectures such as the Cypress PSoC family of MCUs integrate a wide range of capabilities, including MCU cores like the Cortex-M0, programmable analog blocks (PAB), programmable digital blocks (PDB), programmable interconnect and routing, a wide range of interfaces and peripherals, and advanced capabilities such as capacitive touch sensing. These architectures have many advantages over traditional microcontrollers and can substantially reduce design time and system bill of materials (BOM) cost.Īs the complexity of programmable system-on-chip architectures and their MCU increases, so do the issues that can occur at each stage of design.